Layer Reassignment for Antenna E ectMinimization in 3 - Layer Channel Routing

As semiconductor technology enters the deep submicron era, reliability has become a major challenge in the design and manufacturing of next generation VLSI circuits. In this paper we focus on one reliability issue-the antenna eeect in the context of 3-layer channel routing. We rst present an antenna effect model in 3-layer channel routing and, based on this, an antenna eeect cost function is proposed. A layer reassignment approach is adopted to minimize this cost function and we show that the layer reassignment problem can be formulated as a network bipartitioning problem. Experimental results show that the antenna eeect can be reduced considerably by applying the proposed technique. Compared with previous work, one advantage of our approach is that no extra channel area is required for antenna eeect minimization. We show that layer reassignment technique can be used in yield-related critical area minimization in 3-layer channel routing as well. The trade-oo between these two objectives is also presented. Continued advances in IC technology along with the development of packaging technologies with superior thermal characteristics enable an increase in the level of integration of VLSI systems. In this process, the aggressive scaling of device and interconnect dimensions has played, and in the foreseeable future will still play, an important role in achieving signiicant improvements in VLSI performance and circuit density. However, scaling has a detrimental eeect on reliability due to increase in current density, electric eld, leakage currents and oxide breakdown 1]. As a result, reliability has become a major issue and challenge in the design and manufacturing of next generation deep-submicron VLSI circuits 2, 3, 4, 5]. In this paper, we focus on the antenna eeect 6, 7, 8, 9], one of the important reliability issues in today's VLSI systems, in the routing stage of VLSI design. The antenna problem is a side eeect of various plasma-based manufacturing processes such as etching, etc. These plasma-based processes are widely used to get the ne feature size of modern IC. Plasma etchers or ion implanters can induce a voltage into isolated leads, overstressing thin gate oxides. The leads (polysilicon or metal) act like an antenna to collect charges and the accumulated charges may result in oxide breakdown. These charges may also have a negative eeect on hot-carrier device aging lifetime 10]. As device scaling goes on, the oxides of new devices are getting thinner and thinner and, as a result, the problem of …